A comparison with related work on UDP/IP core implementations shows that our implementation is significantly more efficient in terms of resource utilization and performance. The UDP/IP core is available as open-source code. Furthermore, this property also allows for initiating packet transmission immediately, i.e., the UDP/IP core can start a transmission without the requirement of receiving, storing, and processing user data beforehand. An observation regarding the internet checksum algorithm, allows us to reduce the hardware requirements for computing the checksum. To this end, we present the design of an efficient UDP/IP core for PC-FPGA communication that has been designed to occupy a minimum amount of hardware resources on the FPGA. While PCI Express represents the currently fastest and most expensive solution to connect a FPGA to a general purpose CPU, there exist several applications with I/O requirements for which Gigabit Ethernet is sufficient. Input/Output (I/O) speeds can become a bottleneck and directly affect the performance of a reconfigurable accelerator since the chip will idle when there are no data available.

As FPGAs become larger and more powerful, they are increasingly used as accelerator devices for compute-intensive functions.

Serial communication pdf